1. Field of the Invention
The present invention relates to a semiconductor structure and a method of forming the same, and more particularly to a semiconductor structure integrating a power metal-oxide-semiconductor field effect transistor (power MOSFET) and a Schottky diode and a method of forming the same.
2. Description of Related Art
Power metal-oxide-semiconductor field effect transistors (power MOSFETs) are widely applied to switching devices such as power supplies, rectifiers, low-voltage motor controllers and the like. FIG. 1 illustrates a schematic cross-sectional view of a conventional power MOSFET. Referring to FIG. 1, an N-type epitaxial layer 12 is disposed on an N-type heavily-doped substrate 10. A gate 16 is disposed in the N-type epitaxial layer 12. A P-type body layer 14 is disposed in the N-type epitaxial layer 12 beside the gate 16. An N-type heavily-doped region 18 is disposed in the P-type body layer 14 beside the gate 16. A dielectric layer 20 is disposed on the gate 16 and the N-type heavily-doped region 18. A source metal layer 22 is disposed on the dielectric layer 20 and electrically connected to the N-type heavily-doped region 18. A drain metal layer 24 is disposed on the other side of the N-type heavily-doped substrate 10.
Along with an increasing demand for notebook computers and portable products, designs for sync-FETs having low output voltage, low forward voltage drop, low power loss and fast reverse recovery are required. However, due to the inherent PN diode between the P-type body layer 14 and the N-type epitaxial layer 12, the aforementioned requirements are hard to satisfy.
One known method is to integrate a power MOSFET with a Schottky diode to meet the above requirements. The current technology includes two types: silicon-in-one-package (SiP) and system-in-one-chip (SOC). The SiP places a power MOSFET in parallel with a Schottky diode. The formation process is simple, but the bonding wire connecting the power MOSFET and the Schottky diode produces parastitic inductances, so as to limit the overall efficiency. Although the SOC solves the parastitic inductances, the cell pitch thereof is relatively high (greater than 2 μm), so that the cell density can not be enhanced.